1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to complementary metal oxide semiconductor (CMOS) image sensors.
2. Related Art
CMOS imagers have been greatly improved and have been increasingly used in diverse and demanding applications. A typical CMOS imager comprises a focal plane array of pixel cells or pixels, where each pixel comprises a light detection component such as a photodiode, a photo gate, or a photoconductor. Each pixel also has a readout circuit that is connected to its light detection node and may also include a sample-and-hold circuit for electronic shutter control, either before or after the readout circuit. The CMOS imager pixel cell may include at least one transistor for transferring charge from a charge accumulation region of the substrate to the light detection node, which can be a floating diffusion node, and a transistor for resetting the light detection node to a predetermined charge level prior to charge transfer.
A widely used Active Pixel Sensor (APS) is the 3-Transistor (3T) design which comprises a photodiode that is typically reversed-biased, a reset transistor, an amplifier transistor, and a select transistor that connects the pixel to the column bus and allows the signal transfer from the pixel to the column amplifier. This APS design suffers from Fixed Pattern Noise (FPN), kTC Reset noise, and 1/f noise (for low frame rates), and when normally operated provides, performance in the range of 40 to 20e− noise with proper FPN rejection and is dominated by kTC Reset noise.
In order to reduce the kTC noise that afflicts the 3T APS, an APS design having four transistors (4T) with pinned photodiode has been often used. The 4T APS comprises a pinned photo diode that is typically fully depleted, a transfer transistor which provides Correlated Double Sampling (CDS) functionality connected to the light detection node, a reset transistor, an amplifier transistor which could be, e.g., a Source Follower (SF) or an inverting amplifier that converts the integrated photocharge into a voltage and transfers the voltage to the column bus when selected, and a select transistor that connects the pixel to the column bus and allows the signal transfer from the pixel to the column buffer. Two sampling operations are performed. First, the reset level voltage (VRESET) is transferred to the column buffer while the column buffer sample-and-hold (SH) is clamped to a known voltage (VCLAMP). The transfer transistor is off, and the pinned photodiode acts as a memory for the integrated charge. After the clamp is released and the transfer switch is closed, the signal corresponding to the entire integrated charge stored on the pinned photodiode is transferred to the column buffer SH providing kTC reduction. A 4T APS with a typical column buffer circuitry that support CDS is depicted in FIG. 1A, with an associated timing diagram in FIG. 1B, both of which will be described below.
However, the widely used 4T Pinned Photodiode APS circuit, while reducing the kTC noise and fixed pattern noise (FPN) via the CDS operation and circuitry, suffers from several issues. The first problem is that a pinned photodiode is not available in a standard CMOS process. It is of limited availability (i.e., many fabs do not provide it) and of a higher cost. The second problem is a lowered dynamic range due to the limited charge storage capacity of a fully depleted pinned photodiode. Lastly, the noise reduction, reported to be at best around 3e−, is still not sufficient for applications that require sub-election noise.
To overcome the issues related to the pinned photodiode, another approach of performing the CDS outside the CMOS pixel array (also referred to as “off-chip” CDS) has been widely used. In this approach, a conventional 3T APS and column buffer can be used. The 3T APS comprises a photodiode that is typically reversed biased, a reset transistor, an amplifier transistor (typically a Source Follower), and a row select transistor. The column buffer typically contains a sample-and-hold transistor, a sample-and-hold capacitor, a driver amplifier, and a column select transistor. The pixel is read twice sequentially. The first time is at the end of integration period, and the second time is after the photodiode reset. The reset sample is then subtracted from the corresponding signal level in a circuit that resides off the CMOS pixel array, thus providing the kTC and FPN reduction.
However, the off-chip CDS technique has several problems. The first is 1/f noise due the time gap between the reset sampling and the signal sampling. 1/f noise manifests itself as a temporary change in the threshold of the amplifier MOSFET. The 1/f noise becomes the dominant noise source as the frame rate decreases, in particular frame rates below 100 Hz. In addition, faster readout circuitry is required to provide for the double readout. This may increase the noise band and may increase price and complexity. As with the on-chip method, the best results have not surpassed 2-3e−. Thus, both APS with on-chip and off-chip CDS do not achieve the ultra low noise of sub-electron that is required for extreme applications, such as scientific, astronomy, night vision, and such, where ultra low noise Charge Coupled Devices (CCD) are dominant.